Macromodeling CMOS circuits for event driven simulation

Author

Trotter, J. Donald ; Saripella, Satish ; Pidugo, N. ; Ledlow, Dallas L. ; Kapoor, Deepk

Author_Institution

Microsystems Prototyping Lab., Mississippi State Univ., MS, USA

fYear

1994

fDate

19-23 Sep 1994

Firstpage

174

Lastpage

177

Abstract

Using a piece-wise linear source for modeling the input transitions, the logic delays and output transition times are characterized and accurately macromodeled with errors typically less than 1%. Two different logic levels are used at the 70% and 30% points in the transitions to define the “logic events” to circumvent characterized negative delay times. Input capacitance characterization which includes the Miller effect is described. Comparisons of HSpice simulations versus the event simulations for example logic blocks typically result in differences of less than 10%

Keywords

CMOS logic circuits; SPICE; circuit analysis computing; delays; discrete event simulation; hardware description languages; logic CAD; piecewise-linear techniques; CMOS circuits; HSpice simulations; Miller effect; VHDL; characterized negative delay times; event driven simulation; input capacitance characterization; input transitions; logic blocks; logic delays; logic levels; macromodeling; output transition times; piece-wise linear source; CMOS logic circuits; Capacitance; Circuit simulation; Discrete event simulation; Equations; Piecewise linear techniques; Power supplies; Propagation delay; Semiconductor device modeling; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404582

Filename

404582