DocumentCode
3017090
Title
T1: Design for Manufacturability
Author
Zorian, Yervant ; Carballo, Juan-Antonio
Author_Institution
Virage Logic, USA
fYear
2005
fDate
18-21 Dec. 2005
Abstract
In addition to designing the functionality, today’s SOC necessitates designing for manufacturability, yield and reliability. Such requirements are fundamentally transforming the current SoC design methodology techniques for enhancing manufacturability, yield and reliability or "DFX" to include yield enhancement techniques, resolution enhancement techniques, new or restricted design rules, variability-aware design, and the addition of a special family of embedded IP blocks, called infrastructure IP blocks. The latter blocks are meant to ensure manufacturability of the SoC and to achieve adequate levels of yield and reliability. The infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This tutorial analyzes the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of the above DFX techniques. Then, it concentrates on several examples of each of these techniques.
Keywords
Conferences; Design engineering; Design for testability; Design methodology; Electronic design automation and methodology; Logic design; Logic testing; Manufacturing; Reliability engineering; Venture capital;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2005. Proceedings. 14th Asian
ISSN
1081-7735
Print_ISBN
0-7695-2481-8
Type
conf
DOI
10.1109/ATS.2005.103
Filename
1575390
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