High speed stress tolerant 1.6 V – 3.6 V low to high voltage CMOS level shift architecture in 40 nm

An architecture for the scalable speed and multiple supply voltage range of 1.6 V to 3.6 V, low voltage to high voltage level shifter has been proposed. The buffer containing the level shifter is fabricated in 40 nm CMOS process by thin oxide (32 Å thick) devices whose stress limit is 1.98 V (max). The technique generates a set of dynamic differential bias signals as a function of input data sequence, output state of the level shifter and the supply voltage for a given process and temperature to ensure the reliable operation of the level shift stage. The measurement results confirmed successful operation at 40 Mbps with 10 pF load on IO pad, with multiple supplies, 1.8 V - 2.7 V - 3.6 V.