• DocumentCode
    3017615
  • Title

    Circuit Independent Weighted Pseudo-Random BIST Pattern Generator

  • Author

    Yu, Chaowen ; Reddy, Sudhakar M. ; Pomeranz, Irith

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa Univ., IA
  • fYear
    2005
  • fDate
    21-21 Dec. 2005
  • Firstpage
    132
  • Lastpage
    137
  • Abstract
    This paper describes a circuit independent weighted pseudo random BIST pattern generator based on bit-flipping. The circuit dependent data is stored in memories so that different circuits can use the same BIST structure by only changing the data in the memories. New approaches are proposed for compressing and storing the bit-flipping data. Experimental results show that the proposed method reduces the size of the memory considerably while using similar test lengths as a recent method based on bit-fixing
  • Keywords
    automatic test pattern generation; built-in self test; logic testing; bit-fixing; bit-flipping data compression; bit-flipping data storage; circuit pattern generator; independent pattern generator; memory data; pseudorandom BIST pattern generator; weighted pattern generator; Automatic testing; Built-in self-test; Chaos; Circuit faults; Circuit testing; Cities and towns; Electrical fault detection; Fault detection; Logic design; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2005. Proceedings. 14th Asian
  • Conference_Location
    Calcutta
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-2481-8
  • Type

    conf

  • DOI
    10.1109/ATS.2005.37
  • Filename
    1575419