Micro architecture coverage directed generation of test programs

In this paper we demonstrate a method for generation of assembler test programs that systematically probe the architecture of a PowerPC superscalar processor. We show innovations such as ways to make small models for large designs, predict, with cycle accuracy the movement of instructions through the pipes (taking into account stalls and dependencies) and generation of test programs such that each reaches a new architectural state. We compare our method to the established practice of massive random generation and show that the quality of our tests, as measured by transition coverage, is much higher. The main contribution of this paper is not in theory as the theory has been discussed in previous papers, but in describing how to translate this theory into practice in a practical way a task that was far from trivial