DocumentCode
3018260
Title
Efficient Test Compaction for Pseudo-Random Testing
Author
Zhang, Sheng ; Seth, Sharad C. ; Bhattacharya, Bhargab B.
Author_Institution
Dept. of Comput. Sci. & Eng., Nebraska Univ., Lincoln, NE
fYear
2005
fDate
21-21 Dec. 2005
Firstpage
337
Lastpage
342
Abstract
Compact set of 3-valued test vectors for random pattern resistant faults are covered in multiple test passes. During a pass, its associated test cube specifies certain bits in the scan chain to be held fixed and others to change pseudo -randomly. We propose an algorithm to find a small number of cubes to cover all the test vectors, thus minimizing total test length. The test-cube finding algorithm repeatedly evaluates small perturbations of the current solution so as to maximize the expected test coverage of the cube. Experimental results show that our algorithm covers the test vectors by test cubes that are one to two orders of magnitude smaller in number with a much smaller increase in the percentage of specified bits. It outperforms comparable schemes reported in the literature
Keywords
built-in self test; integrated circuit testing; built-in testing; pseudo-random testing; random pattern resistant faults; scan chain; test compaction; test cube; test-data compression; Compaction; Logic testing; Test compaction; built-in testing.; pseudo-random testing; test-data compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2005. Proceedings. 14th Asian
Conference_Location
Calcutta
ISSN
1081-7735
Print_ISBN
0-7695-2481-8
Type
conf
DOI
10.1109/ATS.2005.55
Filename
1575452
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