Statistical device simulation of intrinsic parameter fluctuation in 16-nm-gate n- and p-type Bulk FinFETs

Author

Yu-Yu Chen ; Wen-Tsung Huang ; Sheng-Chia Hsu ; Han-Tung Chang ; Chieh-Yang Chen ; Chin-Min Yang ; Li-Wen Chen ; Yiming Li

Author_Institution

Dept. of Electr. & Comput. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2013

fDate

5-8 Aug. 2013

Firstpage

442

Lastpage

445

Abstract

In this paper, we estimate the influence of random dopants (RDs), interface traps (ITs), and random work functions (WKs) using the experimentally calibrated 3D device simulation on DC characteristic of high-κ / metal gate n- and p-type bulk fin-typed field-effect-transistors. We further study these intrinsic parameter fluctuations´ impact on drain induced barrier lowering (DIBL). The main findings of this work show the RDF and WKF on n-type device are larger than that of p-type one. The DIBL is dominated by the number of random dopants.

Keywords

MOSFET; doping profiles; interface states; quantum theory; semiconductor device models; work function; drain induced barrier lowering; field effect transistors; high-k metal gate devices; interface traps; intrinsic parameter fluctuation; n type bulk FinFET; p type bulk FinFET; random dopants; random work functions; statistical device simulation; FinFETs; Fluctuations; Logic gates; Metals; Resource description framework; Semiconductor process modeling; Three-dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanotechnology (IEEE-NANO), 2013 13th IEEE Conference on

Conference_Location

Beijing

ISSN

1944-9399

Print_ISBN

978-1-4799-0675-8

Type

conf

DOI

10.1109/NANO.2013.6720994

Filename

6720994