An asynchronous parallel neuromorphic ADC architecture

A new parallel ADC architecture is presented which makes use of neuromorphic principles to be fast, accurate, and robust to noise and circuit mismatch. The architecture uses spiking integrate-and-fire neurons as base elements, with lateral inhibition to decohere the parallel pathways, and alternate on-and off-triggered paths to maintain a constant spike rate. Results from a proof-of-concept circuit reinforce the analytical conclusion that this circuit can make a practical ADC.