Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA

W-CDMA offers variable spreading factor and multiple codes per user to enable features like high data rates and multiple services for the same connection. To do so, rake receiver architecture for W-CDMA should be configurable such that hardware is utilized optimally at varying requirements. Additionally, architecture for downlink receiver should consume as less power as possible. In this paper, four different architectures for rake receiver are designed and implemented on FPGA. They are compared for area, frequency and power requirements. We propose a new ´Time Multiplexed Parallel Rake´ architecture which achieves this objective by two ways. First, it exploits parallelism by processing four chip samples at a time and second, it shares resources for multi code operation by despreading the input samples sequentially in time for each code. The algorithmic correctness of various architectures was first checked by developing a MATLAB model using Simulink blocksets libraries and HDL Co-simulation using Xilinx System Generator. The architectures were implemented on Xilinx Virtex II FPGA family.