• DocumentCode
    3019669
  • Title

    An approach to constructing reversible multi-qubit benchmarks with provably minimal implementations

  • Author

    Jegier, Jerzy ; Kerntopf, Pawel ; Szyprowski, Marek

  • Author_Institution
    Orange Labs. Poland, Warsaw, Poland
  • fYear
    2013
  • fDate
    5-8 Aug. 2013
  • Firstpage
    99
  • Lastpage
    104
  • Abstract
    This paper reports on a method of the construction of new difficult benchmarks for reversible logic synthesis. It is shown how to extrapolate 3- and 4-variable reversible functions implemented by gate count minimal circuits having regular structure. In this way sequences of reversible functions of an arbitrary number of variables have been constructed for which we have built minimal circuits implementing them. For two example sequences of functions we applied the synthesis tool Revkit trying different synthesis algorithms. The outcome shows a large gap between the circuits synthesized by the tool and the ones proved minimal by construction.
  • Keywords
    logic circuits; logic gates; network synthesis; 3-variable reversible functions; 4-variable reversible functions; Revkit synthesis tool; circuit synthesis; gate count; minimal circuits; regular structure; reversible logic synthesis; reversible multiqubit benchmarks; Benchmark testing; Boolean functions; Cost function; Data structures; Libraries; Logic gates; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanotechnology (IEEE-NANO), 2013 13th IEEE Conference on
  • Conference_Location
    Beijing
  • ISSN
    1944-9399
  • Print_ISBN
    978-1-4799-0675-8
  • Type

    conf

  • DOI
    10.1109/NANO.2013.6721041
  • Filename
    6721041