• DocumentCode
    3019979
  • Title

    A “design for verification” methodology

  • Author

    Sforza, F. ; Battu, L. ; Brunelli, M. ; Castelnuovo, A. ; Magnaghi, M.

  • Author_Institution
    CR&D, STMicroelectron., Milan, Italy
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    50
  • Lastpage
    55
  • Abstract
    New tools are becoming available on the market that help alleviate the problem and improve the quality of functional verification of today´s complex systems. A methodology that makes use of such tools is described and compared to the traditional approach followed in the context of a specific project. The scope is limited to functional verification but spans from block- to system level
  • Keywords
    application specific integrated circuits; circuit simulation; formal verification; industrial property; integrated circuit design; logic CAD; IC design; IP reuse; SoC; block-level; design for verification; emulation; functional verification; system level; Consumer electronics; Design methodology; Emulation; Fabrication; Memory management; Project management; Prototypes; Switches; Testing; Virtual prototyping;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2001 International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    0-7695-1025-6
  • Type

    conf

  • DOI
    10.1109/ISQED.2001.915205
  • Filename
    915205
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3019979