A power management architecture for fast per-core DVFS in heterogeneous MPSoCs

Author

Höppner, Sebastian ; Shao, Chenming ; Eisenreich, Holger ; Ellguth, Georg ; Ander, Mario ; Schüffny, René

Author_Institution

Fac. of Electr. Eng. & Inf. Technol, Tech. Univ. Dresden, Dresden, Germany

fYear

2012

fDate

20-23 May 2012

Firstpage

261

Lastpage

264

Abstract

This paper presents a power management architecture for MPSoCs that allows fast switching between multiple onchip supply voltage levels per core. Operation is based on distinct scenarios for power-up and supply level change, with individual numbers of pre-charge switches for supply noise reduction. The power management controller is highly configurable for adaption to a wide range of supply network parasitics in heterogeneous MPSoCs. This architecture has been validated by measurements in 65nm CMOS technology. Power-up and DVFS level changes can be performed in less than 20ns with reduced parasitic voltage drop of active cores.

Keywords

CMOS integrated circuits; multiprocessing systems; system-on-chip; CMOS technology; dynamic voltage and frequency scaling; heterogeneous MPSoC; onchip supply voltage levels; parasitic voltage drop; per core DVFS; power management architecture; power management controller; power-up level changes; precharge switches; size 65 nm; supply network parasitics; supply noise reduction; Clocks; Computer architecture; Switches; Switching circuits; System-on-a-chip; Voltage control; Voltage measurement; DVFS; GALS; MPSoC;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Conference_Location

Seoul

ISSN

0271-4302

Print_ISBN

978-1-4673-0218-0

Type

conf

DOI

10.1109/ISCAS.2012.6271840

Filename

6271840