Modelling and designing reliable on-chip-communication devices in MPSoCs with real-time requirements

Due to continuous technology downscaling modern MPSoCs become more and more susceptible to the occurrence of internal errors in computational cores as well as in the on-chip-communication infrastructure. The usage of appropriate techniques is necessary to counteract these errors and thus preventing them from originating a system failure. In this paper we will explore the impact of fault tolerance mechanisms for on-chip communication components in real-time systems. Therefore we will introduce a behavioural model of on-chip communication including a simple simulation framework that can easily be adapted to existing system-on-chip bus architectures. Based on that model several simulations will be performed to determine the reliability of an exemplary on-chip-bus. Our experimental results show that design decisions concerning fault tolerance strongly rely on platform and application characteristics like transmission speed or communication amount.