A fast wake-up power gating technique with inducing a balanced rush current

Power gating technique is important for saving the leakage power, especially for the very deep-submicron system-on-a-chip designs. Although the multi-threshold voltage CMOS (MTCMOS) technology can enable us to cut down the leaky path easily, the induced power/ground bounce is getting worse and can not wake up from power down mode quickly. In this paper, we propose a new concept of power gating technique by balancing the variations of rush current to accelerate the wake-up procedure for a given power/ground bounce specification. Performance evaluations of a 40-bit ALU circuit using the TSMC 0.18μm CMOS technology show that our proposed power gating technique can achieve a 10.23% reduction in wake-up time while keeping the power bounce specification, as compared with the conventional power gating technique.