A ΔΣ-cyclic hybrid ADC for parallel readout sensor applications

In this paper, an ADC for parallel readout to convert large amount data in sensor applications is proposed. The ADC achieves small area and low power consumption by using two-step conversion. A 1^st-order ΔΣ ADC converts coarse bits and then a cyclic ADC converts fine bits. An operational amplifier, comparators, capacitors, and switches used in the ADCs are efficiently shared to reduce power consumption and area. The proposed ADC has simple switching sequence, large tolerance to comparator offset and shared reference voltage between the coarse and fine ADCs. The designed circuit was fabricated in 0.18 μm CMOS using a 1.8 V supply voltage. It consumes 24 μW with 5 MHz clock speed. The measurement results show that SNR is varied from 47.89 to 57.58 dB according to the number of oversampling at 1^st-order ΔΣ ADC.