Pipelined FIR filter architecture and increasing performance of decision-feedback equalizer

In this paper, we first present a procedure to efficiently use Booth-encoding-based input decomposition scheme for FIR filter implementations. We also show that the high-order/high-speed FIR filter architectures usually have unavoidable pipelining delays, and that they add to the feedback loop delay of the decision-feedback equalizers. The added delay degrades the performance of the equalizer for strong near-ISI signals. Finally, we present a new decision-feedback equalizer architecture which functions perfectly even though strong near-ISI signals exist in the channel