Very high speed and low voltage open-loop dual edge triggered sample and hold circuit in 0.18μm CMOS technology

A very high speed and low voltage open-loop dual edge triggered sample and hold (S/H) circuit is proposed. Using a high speed and low voltage multiplexer (MUX) and employing simple and efficient switches the proposed sample and hold circuit can operate with a sampling rates of about 5 GS/s making it suitable for high-speed analog-to-digital converters and wired-line communication systems. Designed in a 0.18μm CMOS process and under a supply voltage of 1 V, it consumes approximately 106 μW for a 125 MHz input sinusoidal signal with a 0.8V peak-to-peak swing at mentioned sampling rate using a 2.5 GHz clock signal.