Implementation of a highly scalable architecture for fast inversion of triangular matrices

In this paper, an FPGA implementation of a novel and highly scalable hardware architecture for fast inversion of triangular matrices is presented. An integral part of modem signal processing and communications applications involves manipulation of large matrices. Therefore, scalable and flexible hardware architectures are increasingly sought for. In this paper, the traditional triangular shaped array architecture with n(n+l)/2 communicating processors, with n being the number of inputs, is mapped to a linear structure with only n processors. The linear and the triangular shaped architectures are compared in aspect of area consumption, latencies, and maximum clocking speed. This paper also show that the linear array structure avoids drawbacks such as non-scalability, large area, and large power consumption. The implementation is based on a numerically stable recurrence algorithm, which has excellent properties for hardware implementation.