High-speed parallel VLSI-architecture for the (24,12) Golay decoder with optimized permutation decoding

Author

Cao, Weixun

Author_Institution

Fraunhofer-Inst. for Integrated Circuits, Erlangen, Germany

Volume

4

fYear

1996

fDate

12-15 May 1996

Firstpage

61

Abstract

An area-efficient parallel VLSI-architecture for the (24,12,8) Golay decoder with an optimized permutation decoding technique based on Wolfmann´s algorithm is presented. The decoder uses a look-ahead error-correction structure and a carry-save computation to obtain the highspeed implementation. The hardware complexity was greatly reduced by using a high computation regularity which maps the cyclic syndrome calculation efficiently on a parallel architecture. It is shown that this new architecture for the Golay decoder can be easily implemented in CMOS technology to operate at a data rate above 1 Gbit/s

Keywords

CMOS digital integrated circuits; VLSI; decoding; digital signal processing chips; error correction codes; field programmable gate arrays; parallel architectures; (24,12,8) Golay decoder; 1 Gbit/s; CMOS technology; Wolfmann algorithm; area-efficient VLSI architecture; carry-save computation; cyclic syndrome calculation mapping; hardware complexity reduction; high computation regularity; high-speed VLSI architecture; look-ahead error-correction structure; optimized permutation decoding; parallel VLSI architecture; Bit error rate; CMOS technology; Concurrent computing; Decoding; Error correction; Error correction codes; Hardware; Parallel architectures; Parallel processing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.541901

Filename

541901