• DocumentCode
    302708
  • Title

    Data-controlled delays in the asynchronous design

  • Author

    Varshavsky, Victor ; Marakhovsky, Vyacheslav ; Tsukisaka, Masayuki

  • Author_Institution
    Aizu Univ., Japan
  • Volume
    4
  • fYear
    1996
  • fDate
    12-15 May 1996
  • Firstpage
    153
  • Abstract
    Asynchronous design technique has an approach of using padding delays to produce signals of transient process completion. In order to increase the efficiency of this approach, we suggest to use data-controlled incorporated delays in the cases when the variations of transient process durations are determined by the sets of input signal values. The control over the value of an incorporated delay is illustrated by an example of asynchronous adder design. The results of PSPICE simulation confirm the efficiency of this approach
  • Keywords
    asynchronous circuits; PSPICE simulation; adder; asynchronous design; data-controlled delay; padding delay; transient process; Adders; Circuits; Clocks; Delay; Organizing; SPICE; Signal design; Signal processing; Synchronization; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
  • Conference_Location
    Atlanta, GA
  • Print_ISBN
    0-7803-3073-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.1996.541922
  • Filename
    541922