A general realization scheme for 2-D digital transfer functions

Because of the inherent impossibility of factorizing arbitrary 2-D polynomials, all realization techniques for the general 2-D digital transfer function presented so far deal with the realization of such functions as a whole. This paper presents a new realization scheme which is based on realizing multi-input, multi-output subnetworks of multipliers and adders interconnecting 2-D digital subnetworks containing the z- and w-delay elements and possibly multipliers and adders in known configurations. Choise of different digital subnetworks leads to different realizations of the same transfer function. It has also been pointed out that any arbitrary transfer function of the form can always be realized by at most min(2M+N, 2N+M) z- and w-delays.