A pipelined VLSI with module structure design for discrete wavelet transforms

This paper presents an efficient pipelined VLSI architecture for computing the Discrete Wavelet Transform (DWT). The features of the architecture are (1) lower hardware cost, (2) shorter latency, (3) simplex control, (4) regular structure for VLSI implementation and (5) higher output throughput rate. Considering the precision of the transformed data, an accuracy analysis of the architecture has been carried out to determine the appropriate bit-width for fitting the hardware executions. Finally, all components in the architecture are well designed and simulated based on the accuracy requirement