Parallel digital image restoration using adaptive VLSI neural chips

Author

Lee, Ji-Chien ; Sheu, Bing J.

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

fYear

1990

fDate

17-19 Sep 1990

Firstpage

126

Lastpage

129

Abstract

Real-time digital image restoration using massively parallel Hopfield neural chips is presented. An efficient mixed-signal VLSI design with analog circuitry to perform neural computation and digital circuitry to process multiple-bit pixel information greatly reduces the network size. Analog programmable synapse cells of 8 bit accuracy are dynamically refreshed. The gain-adjustable neurons enable electronic annealing to quickly reach global minimum in energy function. A prototype 25-neuron chip occupies a silicon area of 4.6×6.8 mm² in MOSIS 2-μm CMOS process has been designed and tested. The speedup factor for each chip is 90 compared to the Sun-3 workstation. An 100-neuron image-restoration chip is achievable in the industrial-level 1-μm technologies

Keywords

CMOS integrated circuits; application specific integrated circuits; computerised picture processing; neural nets; MOSIS 2-μm CMOS; adaptive VLSI neural chips; analog circuitry; digital circuitry; digital image restoration; electronic annealing; energy function; gain-adjustable neurons; global minimum; mixed-signal VLSI design; multiple-bit pixel information; neural computation; parallel Hopfield neural chips; speedup factor; Analog computers; Annealing; Circuits; Computer networks; Digital images; Image restoration; Neural network hardware; Neurons; Prototypes; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2079-X

Type

conf

DOI

10.1109/ICCD.1990.130181

Filename

130181