Performance Analysis of ClearSpeed´s CSX600 Interconnects

Author

Nishikawa, Yuri ; Koibuchi, Michihiro ; Yoshimi, Masato ; Shitara, Akihiro ; Miura, Kenichi ; Amano, Hideharu

Author_Institution

Keio Univ., Yokohama, Japan

fYear

2009

fDate

10-12 Aug. 2009

Firstpage

203

Lastpage

210

Abstract

ClearSpeed´s CSX600 that consists of 96 Processing Elements (PEs) employs a one-dimensional array topology for a simple SIMD processing. To clearly show the performance factors and practical issues of NoCs in an existing modern many-core SIMD system, this paper measures and analyzes NoCs of CSX600 called Swazzle and ClearConnect. Evaluation and analysis results show that the sending and receiving overheads are the major limitation factors to the effective network bandwidth. We found that (1) the number of used PEs, (2) the size of transferred data, and (3) data alignment of a shared memory are three main points to make the best use of bandwidth. In addition, we estimated the best- and worst-case latencies of data transfers in parallel applications.

Keywords

multiprocessing systems; network-on-chip; parallel processing; performance evaluation; 1D array topology; ClearConnect; ClearSpeed CSX600 interconnect; NoC; Swazzle; many-core SIMD system; network bandwidth; performance analysis; performance factors; processing elements; simple SIMD processing; Bandwidth; Concurrent computing; Delay; Distributed processing; Informatics; Joining processes; Network-on-a-chip; Performance analysis; Pipelines; Topology; CSX600; ClearSpeed; NoC; SIMD; performance evaluation;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Processing with Applications, 2009 IEEE International Symposium on

Conference_Location

Chengdu

Print_ISBN

978-0-7695-3747-4

Type

conf

DOI

10.1109/ISPA.2009.102

Filename

5207934