Novel SER standards: Backgrounds and methodologies

Author

Ibe, Eishi ; Shimbo, Ken-ichi ; Toba, Tadanobu ; Taniguchi, Yoshio ; Taniguchi, Hitoshi

Author_Institution

Production Eng. Res. Lab., Hitachi, Ltd., Yokohama, Japan

fYear

2010

fDate

2-4 June 2010

Firstpage

203

Lastpage

207

Abstract

Standard methods to quantify SER susceptibility in memory devices have been established during 2000-2008. JESD89A issued in 2006 covers a wide variety of test methods for terrestrial neutrons and alpha particles. Spallation and (quasi-) monoenergetic neutron tests are among the best options for the SER tests. The methods, however, are being recognized as getting more inaccurate as device scaling proceeds. SER in logic devices is also getting more serious so that standard testing methods have to be established for logic devices. The new standards may include strategies for mitigation of SERs as well. The backgrounds and methodologies to promote new SER standards for device, chip, board layers are discussed in the present paper.

Keywords

SRAM chips; integrated circuit reliability; integrated circuit testing; logic devices; SER standards; SER susceptibility; SRAM; alpha particles; logic devices; memory devices; monoenergetic neutron tests; single event upset; spallation neutron tests; standard testing methods; terrestrial neutrons; Automotive engineering; Circuit testing; Field programmable gate arrays; Identity-based encryption; Logic devices; Logic testing; Neutrons; Programmable logic arrays; Random access memory; Single event upset; SRAM; multi-cell upset (MCU); multi-node upset (MNU); quasi-monoenergetic neutron; scaling; single event upset (SEU); spallation;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design and Technology (ICICDT), 2010 IEEE International Conference on

Conference_Location

Grenoble

Print_ISBN

978-1-4244-5773-1

Type

conf

DOI

10.1109/ICICDT.2010.5510259

Filename

5510259