Lead-free flip chip solution for 40 nm extreme low-k interconnect system

Lead-free flip chip package production solution for 40 nm technology node with aggressive ELK interconnect scheme and tight bump pitch of 150 μm is demonstrated. The use of LF bump and ELK dielectric in a same electronic component poses severe technical challenges due to the pronounced chip-packaging interaction in the system. In this paper, we reviewed the fundamental treatments to enhance the LF bump reliability. New challenges associated with the introduction of ELK are discussed. A careful optimization of material and layer thickness for each constituent in the flip chip package is the key to mitigate the chip-package interactions and to enable LF in 40 nm ELK interconnect.