• DocumentCode
    3031714
  • Title

    Programming and Timing Analysis of Parallel Programs on Multicores

  • Author

    Yip, Eugene ; Roop, Partha S. ; Biglari-Abhari, Morteza ; Girault, Alain

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Auckland, Auckland, New Zealand
  • fYear
    2013
  • fDate
    8-10 July 2013
  • Firstpage
    160
  • Lastpage
    169
  • Abstract
    Multicore processors provide better power-performance trade-offs compared to single-core processors. Consequently, they are rapidly penetrating market segments which are both safety critical and hard real-time in nature. However, designing time-predictable embedded applications over multicores remains a considerable challenge. This paper proposes the ForeC language for the deterministic parallel programming of embedded applications on multicores. ForeC extends C with a minimal set of constructs adopted from synchronous languages. To guarantee the worst-case performance of ForeC programs, we offer a very precise reachability-based timing analyzer. To the best of our knowledge, this is the first attempt at the efficient and deterministic parallel programming of multicores using a synchronous C-variant. Experimentation with large multicore programs revealed an average over-estimation of only 2% for the computed worst-case execution times (WCETs). By reducing our representation of the program´s state-space, we reduced the analysis time for the largest program (with 43, 695 reachable states) by a factor of 342, to only 7 seconds.
  • Keywords
    C language; embedded systems; multiprocessing systems; parallel programming; reachability analysis; ForeC language; ForeC programs; WCET; average over-estimation; deterministic parallel programming; embedded applications; large-multicore programs; minimal construct set; multicore processors; power-performance; program state-space representation; reachability-based timing analyzer; reachable states; safety-critical embedded systems; synchronous C-language; synchronous languages; timing analysis time reduction; worst-case execution times; worst-case performance; Instruction sets; Multicore processing; Robots; Semantics; Synchronization; WCET analysis; parallel programming; synchronous languages;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application of Concurrency to System Design (ACSD), 2013 13th International Conference on
  • Conference_Location
    Barcelona
  • Type

    conf

  • DOI
    10.1109/ACSD.2013.19
  • Filename
    6598351