• DocumentCode
    3033826
  • Title

    A channel engineering combined with channel epitaxy optimization and TED suppression for 0.15 /spl mu/m n-n gate CMOS technology

  • Author

    Abiko, H. ; Ono, A. ; Ueno, R. ; Masuoka, S. ; Shishiguchi, S. ; Nakajima, K. ; Sakai, I.

  • Author_Institution
    ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
  • fYear
    1995
  • fDate
    6-8 June 1995
  • Firstpage
    23
  • Lastpage
    24
  • Abstract
    A new channel engineering combined with optimization of channel epitaxy and suppression of TED (transient enhanced diffusion) is proposed for a practical 0.15 /spl mu/m n-n gate CMOS technology. An optimized channel profile with small Vth fluctuation provides an nMOS with no reverse short channel effect and a high performance BCpMOS.
  • Keywords
    CMOS integrated circuits; doping profiles; integrated circuit technology; ion implantation; large scale integration; vapour phase epitaxial growth; 0.15 micron; TED suppression; channel engineering; channel epitaxy optimization; n-n gate CMOS technology; optimized channel profile; transient enhanced diffusion suppression; Atomic layer deposition; Boron; CMOS process; CMOS technology; Epitaxial growth; Epitaxial layers; Fluctuations; MOS devices; National electric code; Temperature;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    0-7803-2602-4
  • Type

    conf

  • DOI
    10.1109/VLSIT.1995.520841
  • Filename
    520841
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3033826