DocumentCode
3033923
Title
High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: /spl Psi/) SOI wafer
Author
Horiuchi, M. ; Teshima, T. ; Tokumasu, K. ; Yamaguchi, K.
Author_Institution
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fYear
1995
fDate
6-8 June 1995
Firstpage
33
Lastpage
34
Abstract
An ultra-thin SOI MOSFET capable of operations at a current 1.5 times that of conventional deep sub-micron devices at low voltage is presented. This device is fabricated by a conventional MOS process on novel multi-layered SOI wafers.
Keywords
MOSFET; semiconductor technology; silicon-on-insulator; MOS process; PSI SOI wafer; Si; deep sub-micron device; fabrication; high-current low-voltage operation; multi-layered SOI wafer; parasitic capacitance; poly-Si interlayered SOI wafer; ultra-thin SOI MOSFET; Doping; Electrodes; Grain boundaries; Impurities; Intrusion detection; MOS devices; Parasitic capacitance; Positron emission tomography; Threshold voltage; Ultra large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
0-7803-2602-4
Type
conf
DOI
10.1109/VLSIT.1995.520846
Filename
520846
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