DocumentCode
3034435
Title
A co-design approach for SET mitigation in embedded systems
Author
Lindoso, A. ; Entrena, L. ; Millán, E. San ; Cuenca-Asensi, S. ; Martínez-Álvarez, A. ; Restrepo-Calle, F.
fYear
2011
fDate
19-23 Sept. 2011
Firstpage
489
Lastpage
492
Abstract
We propose a new methodology for hardware/software co-design of embedded systems which is specifically aimed to mitigate SET effects. A hardening infrastructure is used to generate different versions of the design using several combinations of hardware and software hardening which are evaluated with respect to SET effects. The advantages of the proposed approach are demonstrated by means of a case study.
Keywords
hardware-software codesign; radiation hardening (electronics); SET effect mitigation; embedded systems; hardening infrastructure; hardware-software codesign; Circuit faults; Clocks; Hardware; Microprocessors; Redundancy; Registers; Software; Single Event Transient; fault tolerance; radiation effects; soft error;
fLanguage
English
Publisher
ieee
Conference_Titel
Radiation and Its Effects on Components and Systems (RADECS), 2011 12th European Conference on
Conference_Location
Sevilla
ISSN
0379-6566
Print_ISBN
978-1-4577-0585-4
Type
conf
DOI
10.1109/RADECS.2011.6131423
Filename
6131423
Link To Document