Cellular and reentrant layouts for semiconductor wafer fabrication facilities

We study alternative facility layouts for semiconductor wafer fabrication facilities using a process developed for manufacturing 3-dimensional CMOS devices as a research vehicle. Simulation experiments indicate that cellular layouts requiring only modestly higher capital investment can yield significantly lower cycle times in heavily loaded fabs. These results suggest that the savings in operating costs such as inventory holding cost over the life of the process may render the additional capital investment required by the cellular layouts economically justifiable