Module Grouping for Defect Tolerance in Nanoscale Memory

Designing a nanoscale memory system with defect rate as high as 10% poses a significant challenge. Redundancies at various levels have been employed to tolerate the high defect rates. Multiple crossbar modules that share the same address space can be used to build a simple and robust memory architecture to overcome the defects in the crossbar. In this paper, we presents a module grouping scheme for tolerating defects in a nanoscale memory composed of nano-modules. Redundancy at nano-module level with some degree of flexibility in assigning nano-modules is used to achieve defect tolerance. Computer simulation shows that the proposed scheme can construct a functioning memory with up to 45% reduction in the required number of nano-modules as compared to the existing simple redundancy scheme.