• DocumentCode
    3038264
  • Title

    Modeling and Evaluation of Threshold Defect Tolerance

  • Author

    Patitz, Z. ; Park, N.

  • Author_Institution
    Dept. of Comput. Sci., Oklahoma State Univ., Stillwater, OK
  • fYear
    2008
  • fDate
    1-3 Oct. 2008
  • Firstpage
    211
  • Lastpage
    219
  • Abstract
    This paper presents a theoretical study on the threshold defect tolerance level. A new defect level model is proposed and used as a basis for the study in order to facilitate a theoretical modeling and evaluation of defect tolerance under a circumstance in which conventional testing processes are not practically viable. A comprehensive and thorough defect classification and characterization is conducted under specific design constraint when traditional testing is not practically deployable. An approach to an extensive theoretical and parametric compilation and optimization will be introduced in order to reveal a theoretical threshold defect tolerance level at which each choice defect tolerance method and strategy can be justified. The simulation results reveal there exists a theoretical threshold of defect tolerance level that will help guide the test and defect tolerance engineers to identify the optimal and viable testing and defect tolerance level.
  • Keywords
    VLSI; tolerance analysis; VLSI; threshold defect tolerance; Circuit simulation; Circuit testing; Computer science; Costs; Fault tolerant systems; Modeling; Optimization methods; Production; Robustness; Very large scale integration; Defect tolerance; defect level; testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on
  • Conference_Location
    Boston, MA
  • ISSN
    1550-5774
  • Print_ISBN
    978-0-7695-3365-0
  • Type

    conf

  • DOI
    10.1109/DFT.2008.56
  • Filename
    4641175