Error Detect Logic Resulting in Faster Address Generate and Decode for Caches

With the complexity of the integrated circuit designs increasing along with the shrinking of the technologies with each passing generation, the vulnerability of these components increases.The sensitivity to transient faults caused by noise, extra terrestrial rays etc. are a cause of concern and require mitigating circuits in any cutting edge of technology. These problems can affect the storage as well as logic elements. The use of arithmetic residues for error detection is well known. This paper explores the use of residues in 1-hot representations of the base and displacement of the address, which are used to generate the word line in a cache. It reduces the delay in comparison with the traditional decode which has no error detection capabilities. It was a welcome case where the addition of error detection capabilities reduced the delays, in comparison with the traditional way of address base-plus-offset summing and decoding in cache accesses.