• DocumentCode
    3038736
  • Title

    A multi-path fused add-subtract unit for Digital Signal Processing

  • Author

    Tao, Yao ; Deyuan, Gao ; Xiaoya, Fan

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Northwestern Polytech. Univ., Xian, China
  • Volume
    3
  • fYear
    2012
  • fDate
    25-27 May 2012
  • Firstpage
    448
  • Lastpage
    452
  • Abstract
    The task of computing both the summation and difference of a pair of Floating-Point (FP) data is often needed in some Digital Signal Processing (DSP) algorithms and other applications. A basic fused add-subtract unit (FAS) is introduced [1] to perform simultaneously both addition and subtraction operation for a couple of operands and has less hardware overhead than the general approach using two FP adders. In this paper, a novel multi-path FAS unit is presented to accelerate the basic FAS architecture. The implementation results in FP single precision data format show that the multi-path FAS is 48.7% faster and 16.9% smaller than the basic FAS unit.
  • Keywords
    adders; floating point arithmetic; sensor fusion; FP adders; addition operation; digital signal processing algorithms; floating-point data; multipath fused add-subtract unit; subtraction operation; Adders; Computer architecture; Delay; Digital signal processing; Equations; Hardware; Signal processing algorithms; Digital Signal Processing; FAS unit; Floating-Point;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Science and Automation Engineering (CSAE), 2012 IEEE International Conference on
  • Conference_Location
    Zhangjiajie
  • Print_ISBN
    978-1-4673-0088-9
  • Type

    conf

  • DOI
    10.1109/CSAE.2012.6272991
  • Filename
    6272991