A 3.3-V 12 ns 16 Mb CMOS SRAM

Author

Goto, H. ; Ohkubo, H. ; Kondou, K. ; Ohkawa, M. ; Mitani, H. ; Horiba, S.-I. ; Soeda, M. ; Hayashi, F. ; Hachiya, Y. ; Shimizu, T. ; Ando, M. ; Matsuda, Z.

Author_Institution

NEC Corp., Sagamihara, Japan

fYear

1992

fDate

19-21 Feb. 1992

Firstpage

216

Lastpage

217

Abstract

The authors describe a 16 Mbit (2 M*8) SRAM with a 12-ns access time using a 0.4- mu m quadruple-polysilicon, double-metal CMOS technology with TFT (thin-film transistor) load memory cells. An access time of 12 ns is obtained with an optimized rotated memory cell array layout and a read bus midlevel voltage preset scheme (RBMIPS). An on-chip test circuit is included for efficient testing. The test circuit has three modes: redundant rows test, redundant columns test, and 16-bit parallel test.<>

Keywords

CMOS integrated circuits; SRAM chips; VLSI; built-in self test; 0.4 micron; 12 ns; 16-bit parallel test; 2 Mbyte; 3.3 V; 4 Mbit; 8 bit; CMOS SRAM; RBMIPS; TFT load memory cells; ULSI; access time; double-metal; on-chip test circuit; optimized rotated memory cell array layout; quadruple-polysilicon; read bus midlevel voltage preset scheme; redundant columns test; redundant rows test; test modes; testability; thin-film transistor; CMOS technology; Circuit simulation; Circuit testing; Decoding; Delay effects; Large scale integration; National electric code; Random access memory; Read-write memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0573-6

Type

conf

DOI

10.1109/ISSCC.1992.200489

Filename

200489