An asymmetric memory cell using a C-TFT for ULSI SRAMs

Author

Kuriyama, H. ; Okada, T. ; Ashida, M. ; Sakamoto, O. ; Yuzuriha, K. ; Tsutsumi, K. ; Nishimura, T. ; Anami, K. ; Kohno, Y. ; Miyoshi, H.

Author_Institution

Mitsubishi Electric Corp., Hyogo, Japan

fYear

1992

fDate

2-4 June 1992

Firstpage

38

Lastpage

39

Abstract

A compact SRAM memory cell structure using a set of C-TFTs (complementary thin-film transistors) is discussed. A C-TFT is composed of a top-gate N-channel TFT and a bottom-gate P-channel TFT. The proposed cell´s size was reduced to 80% of that of a conventional one at the 16-Mb SRAM level. Also, a stable read operation under a low-supply voltage could be realized by using a C-TFT.<>

Keywords

CMOS integrated circuits; SRAM chips; VLSI; integrated circuit technology; thin film transistors; 16 Mbit; 16-Mb SRAM; C-TFT; ULSI SRAMs; asymmetric memory cell; bottom-gate P-channel TFT; cell size reduction; compact SRAM memory cell structure; complementary thin-film transistors; low-supply voltage; stable read operation; top-gate N-channel TFT; Laboratories; Large Hadron Collider; Large scale integration; Low voltage; MOSFETs; Random access memory; Resistors; Thin film transistors; Ultra large scale integration; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0698-8

Type

conf

DOI

10.1109/VLSIT.1992.200635

Filename

200635