DocumentCode
3042037
Title
A 3.3 V operation nonvolatile memory cell technology
Author
Yoshikawa, K. ; Sakagami, E. ; Mori, S. ; Arai, N. ; Narita, K. ; Yamaguchi, Y. ; Ohshima, Y. ; Naruke, K.
Author_Institution
Toshiba Corp., Kawasaki, Japan
fYear
1992
fDate
2-4 June 1992
Firstpage
40
Lastpage
41
Abstract
The design and performance of a stacked-gate nonvolatile memory (EPROM/flash) cell operated with a 3.3-V/sub cc/ power supply are discussed. It is shown that optimally redesigned 5-V cells with thinner gate oxide reduced V/sub t/, and greater channel width can be operated on a 3.3-V V/sub cc/ should also be applicable to the next generation of 64-Mb devices and beyond.<>
Keywords
EPROM; MOS integrated circuits; VLSI; integrated circuit technology; 3.3 V; VLSI; channel width; design; flash EPROM; flash memories; nonvolatile memory cell technology; operation; performance; redesigned 5-V cells; stacked-gate nonvolatile memory; thinner gate oxide; threshold voltage; CMOS logic circuits; Capacitance; EPROM; Laboratories; Logic devices; Microcontrollers; Microelectronics; Nonvolatile memory; Semiconductor devices; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on
Conference_Location
Seattle, WA, USA
Print_ISBN
0-7803-0698-8
Type
conf
DOI
10.1109/VLSIT.1992.200636
Filename
200636
Link To Document