• DocumentCode
    3042314
  • Title

    Eliminating race conditions in system-level models by using parallel simulation infrastructure

  • Author

    Weiwei Chen ; Che-Wei Chang ; Xu Han ; Domer, Rainer

  • Author_Institution
    Center for Embedded Comput. Syst., Univ. of California, Irvine, Irvine, CA, USA
  • fYear
    2012
  • fDate
    9-10 Nov. 2012
  • Firstpage
    118
  • Lastpage
    123
  • Abstract
    For a top-down system design flow, a well-written specification model of an embedded system is crucial for its successful design and implementation. However, the task of writing a correct system-level model is difficult, as it involves, among other tasks, the insertion of parallelism. In this paper, we focus on ensuring model correctness under parallel execution. In particular, the model must be free of race conditions in all accesses to shared variables, so that a safe parallel implementation is possible. Eliminating race conditions is difficult because discrete event simulation often hides such flaws. In particular, the absence of simulation errors does not prove the correctness of the model. We propose to use advanced conflict analysis in the compiler, fast checking in a parallel simulator, and a novel race-condition diagnosis tool, that not only exposes all race conditions, but also locates where and when such problems occur. Our experiments have revealed a number of dangerous race conditions in existing embedded multi-media application models and enabled us to efficiently and safely eliminate these hazards.
  • Keywords
    discrete event simulation; embedded systems; hazards and race conditions; parallel architectures; program compilers; compiler; discrete event simulation; embedded multimedia application models; embedded system; free of race conditions; parallel execution; parallel implementation; parallel simulation infrastructure; parallel simulator; parallelism insertion; race condition elimination; race-condition diagnosis tool; simulation errors; specification model; system-level models; top-down system design flow; Analytical models; Computational modeling; Data models; Debugging; Encoding; Hazards; Parallel processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Level Design Validation and Test Workshop (HLDVT), 2012 IEEE International
  • Conference_Location
    Huntington Beach, CA
  • ISSN
    1552-6674
  • Print_ISBN
    978-1-4673-2897-5
  • Type

    conf

  • DOI
    10.1109/HLDVT.2012.6418253
  • Filename
    6418253