Wafer-mapping of hot carrier lifetime due to physical stress effects (MOSFET)

Author

MacWilliams, K.P. ; Lowry, L.E. ; Swanson, D.J. ; Scarpulla, J.

Author_Institution

Aerospace Corp., Los Angeles, CA, USA

fYear

1992

fDate

2-4 June 1992

Firstpage

100

Lastpage

101

Abstract

It is pointed out that wafer-mapping of physical stresses by X-ray diffraction of a silicided CMOS process shows regions of both very high and low stress levels. The regions of high stress consistently have increased subthreshold slopes and are much more sensitive to hot-carrier induced threshold voltage shifts. Hot carrier lifetime variations over two orders of magnitude are explicitly shown to correlate with the physical stress level within a given highly stressed wafer. To optimally deliver maximum device performance with high reliability, it is essential that physical stress levels be measured, understood, and minimized.<>

Keywords

CMOS integrated circuits; X-ray diffraction examination of materials; carrier lifetime; hot carriers; insulated gate field effect transistors; semiconductor device testing; stress analysis; stress measurement; MOSFET; X-ray diffraction; high reliability; hot carrier lifetime; hot-carrier induced threshold voltage shifts; physical stress effects; silicided CMOS process; subthreshold slopes; wafer-mapping; CMOS process; Fabrication; Hot carriers; MOSFET circuits; Silicidation; Stress; Threshold voltage; Uncertainty; X-ray diffraction; X-ray imaging;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0698-8

Type

conf

DOI

10.1109/VLSIT.1992.200668

Filename

200668