DocumentCode
3042597
Title
A new CMOS structure for low temperature operation with forward substrate bias
Author
Yamamoto, T. ; Mogami, T. ; Terada, K.
Author_Institution
NEC Corp., Sagamihara, Japan
fYear
1992
fDate
2-4 June 1992
Firstpage
104
Lastpage
105
Abstract
A CMOS structure with a local well contact that allows the application of forward substrate bias for both p- and n-well with a single substrate supply is described. Higher driving capability and smaller short channel effects can be realized without device area increase. A propagation delay of 95 ps/stage at V/sub dd/=1.5 V and a temperature of 77 K was obtained with a 0.4- mu m gate length, which is about 1.5 times faster than that of the conventional CMOS structure.<>
Keywords
CMOS integrated circuits; delays; integrated circuit technology; low-temperature techniques; 0.4 micron; 77 K; 95 ps; CMOS structure; driving capability; forward substrate bias; gate length; local well contact; low temperature operation; propagation delay; short channel effects; Circuits; Inverters; Leakage current; Low voltage; Microelectronics; Power dissipation; Propagation delay; Temperature; Threshold voltage; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on
Conference_Location
Seattle, WA, USA
Print_ISBN
0-7803-0698-8
Type
conf
DOI
10.1109/VLSIT.1992.200670
Filename
200670
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