Energy-optimal signaling and ordering of bits for area-constrained interconnects

Author

Jayaprakash, Sharath ; Mahapatra, Nihar R.

Author_Institution

Dept. of Electr.&Comput. Eng., Michigan State Univ., East Lansing, MI

fYear

2008

fDate

17-20 Sept. 2008

Firstpage

9

Lastpage

12

Abstract

Narrow-width and multiplexed buses are suitable for underutilized interconnects in microprocessors to reduce area/cost with minimal performance overheads. However, due to the interleaving of uncorrelated traffic, they have higher switching activity and energy dissipation compared to demultiplexed buses. We demonstrate the effectiveness of energy-optimal bit signaling and ordering for multi-plexed buses in significantly reducing this energy overhead across SPEC CPU2k benchmarks.

Keywords

integrated circuit interconnections; microprocessor chips; SPEC CPU2k benchmarks; area-constrained interconnects; bit ordering; demultiplexed buses; energy dissipation; energy-optimal bit signaling; energy-optimal signaling; microprocessors; narrow-width buses; performance overheads; switching activity; uncorrelated traffic; underutilized interconnects; CMOS technology; Costs; Encoding; Energy dissipation; Energy efficiency; LAN interconnection; Power engineering and energy; Power system interconnection; Vehicle dynamics; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2008 IEEE International

Conference_Location

Newport Beach, CA

Print_ISBN

978-1-4244-2596-9

Electronic_ISBN

978-1-4244-2597-6

Type

conf

DOI

10.1109/SOCC.2008.4641469

Filename

4641469