DocumentCode
3044544
Title
An automated design method for chip power distribution
Author
Phan, Di ; Berry, Chris ; Malgioglio, Frank ; Wagstaff, Alan
Author_Institution
IBM Syst. Technol. Group, Poughkeepsie, NY
fYear
2008
fDate
17-20 Sept. 2008
Firstpage
361
Lastpage
364
Abstract
This paper reports on a highly effective chip power grid physical implementation method that was applied to a high-performance multi-voltage multi-core processor. The complete chip power build process was automated to prevent flagrant power connection issues and to provide great savings in the overall design cycle.
Keywords
integrated circuit design; microprocessor chips; chip power distribution; multicore processor; power connection; processor design; CMOS technology; Design methodology; Error analysis; Multicore processing; Power distribution; Power grids; Routing; Timing; Transistors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2008 IEEE International
Conference_Location
Newport Beach, CA
Print_ISBN
978-1-4244-2596-9
Electronic_ISBN
978-1-4244-2597-6
Type
conf
DOI
10.1109/SOCC.2008.4641545
Filename
4641545
Link To Document