Forward-looking macro generation and relational placement during high level synthesis to FPGAs

Summary form only given. Incorporating physical information into earlier architectural and logic synthesis stages is highly desirable since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics. We present a forward-looking synthesis methodology in which we weigh all nets in the control data flow graph (CDFG) according to their criticality. We cluster operations in the CDFG into macros while satisfying logical and physical constraints. We perform relational placement on these macros. We have evaluated the proposed approach using a set of benchmark designs by comparing it with the results of a traditional synthesis flow. The results show that our methodology achieves up to 26% improvement in clock frequency without any area overhead, and average 12.7% improvement in critical path delay with no or little place-and-route time overhead.