Exploring the design space for area-efficient embedded VLIW packet processing engine

Author

Najafi, M. Hassan ; Salehi, Mostafa E.

Author_Institution

Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran

fYear

2013

fDate

14-16 May 2013

Firstpage

1

Lastpage

6

Abstract

Today area-efficiency is an important factor in designing embedded systems. This paper presents a design space exploration based on an embedded VLIW processor for finding out the optimum architecture for ever increasing demands of embedded packet-processing applications. In our exploration, we use the VEX toolchain for exploring the effects of memory hierarchy, different architectural configurations, and compiler optimizations on both performance and area. Exploration results will find out the best architecture and compiler optimizations for VLIW embedded packet-processing engines to have area-efficiency as well as time-efficiency.

Keywords

embedded systems; instruction sets; multiprocessing systems; optimising compilers; parallel architectures; VEX toolchain; architectural configurations; area-efficiency; compiler optimizations; design space exploration; embedded VLIW packet processing engine; embedded system; instruction-level-parallelism; memory hierarchy; optimum architecture; time-efficiency; Benchmark testing; Computer architecture; Optimization; Ports (Computers); Registers; Space exploration; VLIW; Area-efficient embedded architecture; Design space exploration; VLIW instruction-level parallelism;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering (ICEE), 2013 21st Iranian Conference on

Conference_Location

Mashhad

Type

conf

DOI

10.1109/IranianCEE.2013.6599548

Filename

6599548