DocumentCode
3045577
Title
Delay defect diagnosis methodology using path delay measurements
Author
Jang, Eun Jung ; Chung, Jaeyong ; Abraham, Jacob A.
Author_Institution
Comput. Eng. Res. Center, Univ. of Texas at Austin, Austin, TX, USA
fYear
2011
fDate
12-14 Dec. 2011
Firstpage
317
Lastpage
320
Abstract
With aggressive device scaling, timing failures have become more prevalent due to manufacturing defects and process variations. When timing failure occurs, it is important to take corrective actions immediately. Therefore, an efficient and fast diagnosis method is essential. In this paper, we propose a new diagnostic method using timing information. Our method approximately estimates all the segment delays of measured paths in a design using inequality-constrained least squares methods. Then, the proposed method ranks the possible locations of delay defects based on the difference between estimated segment delays and the expected values of segment delays. The method works well for multiple delay defects as well as single delay defects. Experiment results show that our method yields good diagnostic resolution. With the proposed method, the average first hit rank (FHR), was within 7 for single delay defect and within 8 for multiple delay defects.
Keywords
delay estimation; integrated circuit testing; least squares approximations; timing; average first hit rank; delay defect diagnosis methodology; estimated segment delay; fast diagnosis method; inequality constrained least squares method; multiple delay defect; path delay measurements; segment delays; single delay defect; timing failure; timing information; Circuit faults; Delay; Integrated circuit modeling; Silicon; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits (ISIC), 2011 13th International Symposium on
Conference_Location
Singapore
Print_ISBN
978-1-61284-863-1
Type
conf
DOI
10.1109/ISICir.2011.6131960
Filename
6131960
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