Using ArchC to model a Hard-PLC processor

The advancing automation of the industrial production requires faster and more efficient programmable logic controllers. Today´s controller architectures based on specialized processors to execute the STL application are at their limits. For any further improvement the architecture of these processors needs to evolve from single core in order execution to a multicore out of order architecture. This step can not occur without additions to the PLC´s instruction set. Therefore a PLC processor instruction set simulation is required that allows a quick evaluation of the effectiveness and efficiency of instruction set changes as well as changes to the processor´s architecture. Current architecture description languages (ADL) allow the fast modeling of these changes with enough flexibility for the planned improvements and provide fast simulation speed. This work presents for the first time an instruction set simulation environment for STL compatible PLC processors using the ADL ArchC as a base for further research.