A ΔΣ fractional-N PLL with fast Auto-Frequency Calibration for CMMB tuners

A ΔΣ fractional-N Phase-Locked Loop (PLL) with fast Auto-Frequency Calibration (AFC) is presented in this paper. The proposed PLL employs a dual-core Voltage Controlled Oscillator (VCO), a programmable Frequency Divider (FD), a Phase/Frequency Detector (PFD), and a replica biased Charge Pump (CP) with static offset current to compensate fractional spur, etc. This PLL is intended for a China Mobile Multimedia Broadcasting (CMMB) TV tuner. The design is implemented in a 0.18-μm CMOS process and occupies an area of 2.1 mm×0.92 mm including the on-chip third-order loop filter and the digital circuits. The simulated power consumption is 10 mA at a 1.8 V supply voltage. The simulation result of the phase noise satisfies the CMMB specification. Also, with the help of a fast AFC scheme, the proposed PLL achieves fast settling performance. The settling time is less than 50 fis in typical case including both coarse tuning and fine tuning.