Non-synchronous control of bit-serial video signal processor array architectures

The synchronous control system used by conventional bit-serial SIMD array processors means that the instruction cycle time must always be long enough for the slowest possible type of cycle. Removing the fixed cycle-time constraint, by using a non-synchronous controller, would allow a significant speedup, as many cycles are much quicker than the slowest type. Simply implementing such a device as an asynchronous architecture is not currently practical for many of the reasons argued in the literature, such as the silicon overhead, so a hybrid approach is required. We evaluate the benefits of such a hybrid, non-synchronous control strategy for a general purpose image and video processing architecture