Memory efficient architectures for 2-D lifting-based discrete wavelet transform: A survey

The goal of this paper is to review recent developments in memory efficient VLSI architectures of the lifting based two dimensional discrete wavelet transform (DWT). The memory requirement and critical path delay are key points determining the efficiency of the architecture. In recent years, architectures have been developed to achieve balance between path delay and memory requirement. Memory requirement is also contributed by methods used for reading the data from the input image. Architectures with various data scanning methods are reviewed in this paper.